
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
An
INTERNAL (3)
ADDRESS
An (7)
An + 1
An + 2
An + 3
An + 4
t SCLD t HCLD
CNTLD
t SCINC t HCINC
CNTINC
t SD t HD
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
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Timing Waveform of Counter Reset (2)
t CYC2
t CH2
t CL2
CLK
t SA t HA
(4)
ADDRESS
An
An + 1
An + 2
INTERNAL (3)
ADDRESS
Ax
A 0
A 1
An
An + 1
t SW t HW
R/ W
CNTLD
t SCLD t HCLD
CNTINC
t SCRST t HCRST
t SCINC t HCINC
CNTRST
DATA IN
(5)
t SD
t HD
D 0
DATA OUT
Q 0
Q 1
Qn
EXECUTE
CNTRST
(6)
WRITE
A 0
READ
A 0
READ
A 1
READ
ADDRESS n
READ
ADDRESS n+1
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NOTES:
1. CE 0, LB , UB , and R/ W = V IL ; CE 1 and CNTRST , MRST , MKLD , MKRD , and CNTRD = v IH.
2. CE 0 , LB , UB = V IL ; CE 1 = V IH .
3. The "Internal Address" is equal to the "External Address" when CNTLD = V IL and equals the counter value when CNTLD = V IH .
4. Addresses do not have to be accessed sequentially since CNTLD = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during CNTRST operation. A READ or WRITE cycle may be coincidental with the counter CNTRST cycle: Address 0000h will be
accessed. Extra cycles are shown here simply for clarification. For more information on CNTRST function refer to Truth Table II.
7. CNTINC = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address
is written to during this cycle.
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